An Efficient Realization Area-Time with Multi Constant Multiplications for Low Power Design
نویسندگان
چکیده
In this paper, critical path of multiple constant multiplication (MCM) block is analysed precisely and optimized for high-speed and low-complexity implementation. A delay model based on signal propagation path is proposed for more precise estimation of critical path delay of MCM blocks than the conventional adder depth and the number of cascaded full adders. A dual objective configuration optimization (DOCO) algorithm is developed to optimize the shift-add network configuration to derive high-speed and low-complexity implementation of the MCM block for a given fundamental set along with a corresponding additional fundamental set. A genetic algorithm (GA)based technique is further proposed to search for optimum additional fundamentals. In the evolution process of GA, theDOCO is applied to each searched additional fundamental set to optimize the configuration of the corresponding shift-add network.
منابع مشابه
Fine-grained Critical Path Analysis and Optimization for Area-time Efficient Realization of Multiple Constant Multiplications
In this paper, a set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and antisymmetrical particular cases are also covered. In last two decades, many efficient algorithms and architectures have been introduced for the design of low complexity bit-parallel Multiple Constant Multiplic...
متن کاملDesign and Implementation of Low Power High Speed VLSI DSP System for Multirate Polyphase Interpolator
Interpolator is an important sampling device used for Multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems. In this paper, an efficient method has been presented to implement low powe...
متن کاملDesign and Synthesis of High Speed Low Power Signed Digit Adders
Signed digit (SD) number systems provide the possibility of constant-time addition, where inter-digit carry propagation is eliminated. Such carry-free addition is primarily a three-step process; adding the equally weighted SDs to form the primary sum digits, decomposing the latter to interim sum digits and transfer digits, which commonly belong to {–1, 0, 1}, and finally adding the tra...
متن کاملAn Efficient Design of Memory-Based Realization of FIR Digital Filter
In the last two decades, many efficient algorithmsand architectures have been introduced for the design of lowcomplexity bit-parallel multiple constant multiplications (MCM)operation which dominates the complexity of many digital signalprocessing systems. On the other hand, little attention has beengiven to the digitserial MCM design that offers alternative lowcomplexityMCM operations albeit at...
متن کاملA New algorithm for multiple constant multiplications with low power consumption
Multiplications are costly operations in FIR filters. But for any given filter, the filter weights are constants. Several techniques have been developed over the years for the efficient realization of constant multiplications by a network of add/subtract-shift operations [6]. Constant multiplication methods are broadly of two types, (i) single constant multiplication (SCM) methods and (ii) mult...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2016